Semiconductor device with multiple emitter contact plugs

ABSTRACT

A semiconductor device, such as a BICMOS, includes a bipolar transistor having at least an emitter region. An emitter electrode is formed on the emitter region. Further, a wiring pattern is formed over the emitter region. A plurality of contact plugs are formed to electrically connect the emitter electrode with the wiring pattern. The contact plugs are partially embedded in the emitter electrode in order to prevent of reduction of the current amplification factor of the bipolar transistor.

BACKGROUND OF THE INVENTION

[0001] This invention relates to a semiconductor device having a bipolartransistor and a method of manufacturing the same, and in particular, toa BiCMOS semiconductor device and a method of manufacturing the same.

[0002] Generally, a semiconductor device often includes a BiCMOSintegrated circuit in which a bipolar transistor and a complimentary MOS(CMOS) transistor are formed on the same chip. Herein, the CMOStransistor is advantageous in structuring a logic circuit while thebipolar transistor is advantageous in constituting a linear circuit suchas an amplifier circuit. The above BiCMOS integrated circuit has bothadvantages of the CMOS transistor and the bipolar transistor.

[0003] Such a BiCMOS integrated circuit often constitutes a SRAM whichhas a memory cell portion and a sense amplifier portion which isarranged at the periphery of the memory cell portion. In this event, thememory cell portion is composed of the CMOS transistors while the senseamplifier portion is composed of the bipolar transistors. Herein, it isto be noted that the SRAM consisting of the BiCMOS will be thereinafterreferred to as a BICMOS SRAM.

[0004] In such a BICMOS SRAM, a MOS transistor region and a bipolartransistor region are placed adjacent to each other via a field oxidefilm. In this event, the MOS transistor has a drain region, a sourceregion and a gate region while the bipolar transistor has a base region,an emitter region and a collector region. Further, an emitter electrodeis formed on the emitter region.

[0005] In this case, the MOS transistor is covered with a firstinsulating layer in the MOS transistor region while the bipolartransistor is covered with a second insulating layer in the bipolartransistor region. Further, a first wiring layer is formed on the firstinsulating layer while a second wiring layer is formed on the secondinsulating layer.

[0006] Herein, the thickness of the second insulating layer in thebipolar transistor region becomes thinner than that of the firstinsulating layer in the MOS transistor region. This thickness differenceis caused by the manufacturing process. Consequently, the height betweenthe bipolar transistor and the second wiring pattern is generallydifferent from the height between the MOS transistor and the firstwiring pattern.

[0007] Under the circumstances, a first contact hole is formed in thefirst insulating layer in the MOS. transistor region by the use of theknown dry-etching process. At the same time, a second contact hole isformed in the second insulating layer in the bipolar transistor regionin the same manner. Further, a first contact plug is embedded in thefirst contact hole while a second contact plug is embedded in the secondcontact hole.

[0008] In this event, the second insulating layer in the bipolartransistor region is quickly etched as compared to the first insulatinglayer in the MOS transistor region. Consequently, the emitter electrodeis excessively or partially etched. Thus, when the emitter electrode isexcessively etched, the characteristic of the bipolar transistor isdegraded.

[0009] Specifically, when the emitter electrode is partially etched, thethickness of the emitter electrode becomes thin. Consequently, the ratioof holes which recombine in the emitter electrode is reduced. As aresult, the base current of the base region is increased. The increaseof the base current reduces the direct current amplification factor ofthe bipolar transistor.

SUMMARY OF THE INVENTION

[0010] It is therefore an object of this invention to provide asemiconductor device which is capable of preventing reduction of adirect current amplification factor in a semiconductor device having abipolar transistor.

[0011] It is another object of this invention to provide a BiCMOSsemiconductor device which is operable at a high speed.

[0012] It is still another object of this invention to provide a methodof manufacturing a semiconductor device or a BiCMOS semiconductor devicewhich is capable of forming contact plugs in insulating layers whichhave different thickness and which are formed in a bipolar transistorregion and a MOS transistor region.

[0013] According to this invention, a semiconductor device includes abipolar transistor having at least, an emitter region. An emitterelectrode is formed on the emitter region. Further, a wiring pattern isformed over the emitter region. With such a structure, a plurality ofcontact plugs are formed to electrically connect the emitter electrodewith the wiring pattern. In this event, the contact plugs are partiallyembedded in the emitter electrode in order to preventing reduction ofthe current amplification factor of the bipolar transistor.

[0014] Further, the semiconductor device (BiCMOS) includes a CMOStransistor which has at least source and drain regions and a bipolartransistor which has at least an emitter electrode and which is arrangedadjacent to the CMOS transistor. In this event, a first insulating layeris formed on the CMOS transistor. Further, a first wiring pattern isformed on the first insulating layer and over the CMOS transistor. Afirst contact plug is formed in the first insulating layer toelectrically connect either one of the source and drain regions with thewiring pattern.

[0015] On the other hand, a second insulating layer is formed on thebipolar transistor. Further, a second wiring pattern is formed on thesecond insulating layer and over the bipolar transistor. A plurality ofsecond contact plugs are formed in the second insulating layer toelectrically connect the emitter electrode with the second wiringpattern.

[0016] In this event, the second contact plugs are partially embedded inthe emitter electrode in order to prevent the reduction of the currentamplification factor of the bipolar transistor.

[0017] In the semiconductor device (BiCMOS), the current amplificationfactor of the bipolar transistor can be suitably determined inaccordance with the purposes by selecting the number of the secondcontact plugs in accordance with the height difference between the firstcontact plug and the second contact plug.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018]FIG. 1 is a sectional view showing a conventional semiconductordevice;

[0019]FIG. 2 a partial plan view showing a bipolar transistor region ofa semiconductor device illustrated in FIG. 1;

[0020]FIG. 3 is a sectional view showing a part of a manufacturingprocess of a semiconductor device according to this invention;

[0021]FIG. 4 is a sectional view showing another part of a manufacturingprocess of a semiconductor device according to this invention;

[0022]FIG. 5 is a sectional view showing a semiconductor deviceaccording to this invention; and

[0023]FIG. 6 a partial plan view showing a bipolar transistor region ofa semiconductor device illustrated in FIG. 5.

DESCRIPTION OF THE PREFERRED EMBODIMENT

[0024] Referring to FIG. 1, a conventional semiconductor device (BiCMOSSRAM) will be first described for a better understanding of thisinvention. The semiconductor device is equivalent to the conventionalsemiconductor device mentioned in the preamble of the instantspecification.

[0025] In a conventional BiCMOS SRAM, an N-type epitaxial layer 3 isformed by the use of the known epitaxial growth process on a P-typesemiconductor substrate 1. Further, a surface of the epitaxial layer 3is divided into a MOS transistor region A and a bipolar transistorregion B by an insulating film 2 for a device separation. In this event,a memory cell portion is structured by the MOS transistor region A whilea peripheral circuit portion is structured by the bipolar transistorregion B. Alternatively, the N-type epitaxial layer 3 may be formed bythe use of the known ion implantation process.

[0026] Moreover, an N-type embedded layer 4 is formed in the bipolartransistor region B. in addition, a P-type intrinsic base-region 6 isformed in the epitaxial region 3 of the bipolar transistor region B andfurther, an N-type emitter diffusion region 11 is formed in the baseregion 6. In this example, an emitter electrode 10 of a polysilicon isplaced on the emitter diffusion region 11.

[0027] On the other hand, a P-type well region 5 is formed in the MOStransistor region A. Further, N⁺-type drain and source regions 8 areformed so as to interpose a channel region 22 therebetween. A gate oxidefilm 23 is deposited on the channel region 22 and further, a gateelectrode 7 is formed on the gate oxide film 23. The gate electrode 7extends on the other region, such as the insulating film 2, forelectrical connection.

[0028] First, second and third oxide silicon films 9, 12 and 13 aredeposited on the gate electrode 7 and further, a ground wiring pattern14 is selectively formed on the third oxide silicon film 13. The groundwiring pattern 14 is covered with a fourth oxide silicon film 15.Thereafter, the first to fourth oxide silicon films are selectivelyetched to form an opening at a position which corresponds to either oneof the source and drain regions 8 in the MOS transistor region A.Further, polysilicon 16 is formed as a resistance so as to electricallycontact with either one of the source and drain regions 8. Successively,fifth and sixth oxide silicon films 17 and 18 are sequentially depositedon the polysilicon 16. Moreover, the surface of the sixth oxide siliconfilm 18 is flattened.

[0029] As illustrated in FIG. 1, the surface of the sixth oxide siliconfilm 18 in the MOS transistor region A is higher than the surface of thesixth oxide silicon film 18 in the bipolar transistor region B. This isbecause the gate electrode 7, the ground wiring pattern 14 and thepolysilicon 16 are placed in the MOS transistor region A in addition tothe insulating layers of the oxide silicon films.

[0030] With such a structure, an Al wiring pattern. 21 is selectivelyformed on the sixth oxide silicon film 18 in the MOS transistor region Aand the bipolar transistor region B. In this event, the Al wiringpattern 21 must be electrically connected to the emitter electrode 10 inthe bipolar transistor region B and either one of the source and drainregions 8 in the MOS transistor region A.

[0031] To this end, contact holes 19 and 20 are formed on either one ofthe source and drain regions 8 and on the emitter electrode 10. Herein,the depth of the contact hole 19 on either one of the source and drainregions is deeper than the depth of the contact hole 20 on the emitterelectrode 10. This is caused by the thickness difference between theinsulating layers in the MOS transistor region A and the bipolartransistor region B.

[0032] As illustrated in FIG. 2, the contact hole 20 in the bipolartransistor region B is formed in a slit shape and has the width of 0.6μm and the length of 8 μm. On the other hand, the contact hole 19 in theMOS transistor region A is smaller than the slit shaped contact hole 20and has a square shape of about 0.5 μm. Further, contact plugs of W areembedded in the above contact holes 19 and 20.

[0033] When the above contact holes 19 and 20 are opened, if contactholes are opened on the basis of only the contact hole 20 in the bipolartransistor region B, the contact hole 19 does not reach the source anddrain regions 8 in the MOS transistor region A. Consequently, the MOStransistor is put into an open state to obtain a defective product. Thisis because the insulating layer in the MOS transistor region A isthicker than the insulating layer in the bipolar transistor region B.

[0034] Therefore, the contact hole 20 in the bipolar transistor region Bmust be opened, in accordance with the depth of the contact hole 19 inthe MOS transistor region A. Consequently, the emitter electrode 10 isexcessively etched. Specifically, the polysilicon of the emitterelectrode 10 is partially etched by the dry-etching process duringopening the contact hole 20. As a result, the thickness of the emitterelectrode 10 itself inevitably becomes thin.

[0035] When the thickness of the emitter electrode 10 is thinned asmentioned above, the ratio of holes which recombine in the polysiliconof the emitter electrode 10 is reduced. Consequently, the base currentlb in the base region 6 is increased. As a result, the direct currentamplification factor (h_(FE)) becomes small with the increase of thebase current Ib. Herein, the direct current amplification factor(h_(FE)) of the bipolar transistor is determined by the ratio betweenthe collector current Ic and the base current Ib (namely, Ic/Ib).

[0036] Taking the above-mentioned problem into consideration, thisinvention provides a semiconductor device which is capable of preventingthe reduction of the the direct current amplification factor of thebipolar transistor in the semiconductor device.

[0037] Referring to FIGS. 3 through 5, description will be made about asemiconductor device according to an embodiment of this invention. Inthe illustrated embodiment, a BICMOS SRAM is shown in the order of themanufacturing steps. Herein, it is to be noted that the same referentialnumbers are attached to the corresponding portions with FIG. 1 in theFIGS. 3 through 5.

[0038] In FIG. 3, a surface of a P-type silicon substrate 1 is dividedinto a MOS transistor region A and a bipolar transistor region B. Amemory cell portion is structured by the MOS transistor region A while aperipheral circuit portion is structured by the bipolar transistorregion B. In this event, the MOS transistor region A constitutes a CMOScircuit.

[0039] Subsequently, an N-type embedded layer 4 of phosphorus is formedin the bipolar transistor region B. Further, an N-type epitaxial layer 3is formed on the silicon substrate 1 in the bipolar transistor region B.On the other hand, a P-well region 5 is formed on the silicon substrate1 in the MOS transistor region A. In this event, the MOS transistorregion A and the bipolar transistor region B are divided by aninsulating film 2 for device separation. Further, a P-type intrinsicregion 6 is formed as a base region in the epitaxial layer 3 of thebipolar transistor region B.

[0040] As illustrated in FIG. 4, a gate oxide film 23 and a gateelectrode 7 are formed on the P-well region 5 by the use of the knownprocess in the MOS transistor region A. Herein, the gate electrode 7 isextended on the oxide silicon film 2 to be electrically connected withthe other devices. Further, an N⁺ diffusion layers 8 are formed in theP-well region 5 to form source and drain regions 8 of the MOStransistor. Subsequently, a first oxide silicon film 9 is deposited onthe gate electrode 7. Thereafter, an emitter contact hole (not shown) isopened in the first oxide silicon film 9 in the bipolar transistorregion B. Next, polysilicon is deposited to form the emitter electrode10. Further, an emitter diffusion layer 11 is formed as the emitterregion in the P-type intrinsic region 6 (base region) by the use of theion implantation and the heat treatment.

[0041] Successively, a second oxide silicon film 12 and a third oxidesilicon film 13 are deposited after the formation of the emitterelectrode 10. Consequently, the emitter electrode 10 is covered with thesecond and third oxide silicon films 12 and 13. At the same time, thegate electrode 7 is also covered with these oxide silicon films 12 and13. Herein, the third oxide silicon film 13 may be formed by TEOS BPSGhaving an excellent reflow characteristic and may have the thickness ofabout 500 nm. The third oxide silicon film 13 serves to flatten thesurface so that no short occurs for a wiring layer during the subsequentwiring process.

[0042] Next, a ground wiring pattern 14 is formed at a predeterminedposition on the third oxide silicon film 13. Further, a fourth oxidesilicon film 15 is deposited on the ground wiring pattern 14.

[0043] Thereafter, a contact hole (thereinafter, referred to as a commoncontact hole) is opened in the first, second, third and fourth oxidesilicon films 9, 12, 13 and 15 to exposed either one of the source anddrain regions 8 in the MOS transistor region A.

[0044] Moreover, a low resistance polysilicon 16 is selectively formedon the fourth oxide silicon film 15 and in the common contact hole sothat the low resistance polysilicon 16 electrically contacts the gateelectrode 7 and the N⁺ diffusion layers 8. Successively, a fifth oxidesilicon film 17 is deposited on the low resistance polysilicon 16.

[0045] Next, as illustrated in FIG. 5, a sixth oxide silicon film 18having the thickness of about 500 nm is deposited on the fifth oxidesilicon film 17. The sixth oxide silicon film 18 may be formed by TEOSBPSG having 13 an excellent reflow characteristic like the third oxidesilicon film 13. The sixth oxide silicon film 18 also serves to flattenthe surface so that no short occurs for the wiring layer.

[0046] Subsequently, contact holes 19 and 20 are opened by thedry-etching in the first, second, third, fourth, fifth and sixth oxidesilicon films 9, 12, 13, 15, 17 and 18. In this example, the contacthole 19 is positioned on the N⁺ diffusion layer 8 while the contact hole20 is placed on the emitter electrode 10. Herein, it is to be noted thatthe thickness of the above oxide silicon film at the position of thecontact hole 19 is thicker than that of the oxide silicon film at theposition of the contact hole 20 as illustrated in FIG. 5. Further, an Alwiring layer 21 is formed on the sixth oxide silicon film 18.

[0047] Moreover, metal plugs of W are embedded in the contact holes 19and 20. The plugs in the contact holes 19 and 20 serves to electricallycontact the Al wiring layer 21 with the N⁺ diffusion layer 8 and theemitter electrode 10.

[0048] Referring to FIG. 6 with together, the relation between theemitter electrode 10 and the contact hole 20 will be described below.The contact hole 20 is positioned below the Al wiring layer 21 and iscomposed of eight via holes 20 a through 20 h as illustrated in FIG. 6.The via holes 20 a through 20 h are arranged in a line and in thelateral direction. In this case, each of the via holes 20 a through 20 hhas a square shape having a size of 0.48 μm×0.48 μm. Further, each ofdistances between the via holes 20 a through 20 h which are adjacent toeach other is set to 0.6 μm.

[0049] When the contact holes 20 illustrated in FIGS. 5 and 6 are formedon the emitter electrode 10 of the polysilicon, the polysilicon of theemitter electrode 10 is partially removed or etched. However, the areaof the removed emitter electrode 10 is small as compared to theconventional case illustrated in FIG. 1. Therefore, the number of theholes which recombine in the polysilicon of the emitter electrode 10 canbe reduced in accordance with the ratio between the area of the contacthole 20 illustrated in FIG. 2 and the total area of the via holes 20 athrough 20 h illustrated in FIG. 6.

[0050] Consequently, the base current Ib can be reduced to increase thecurrent amplification factor h_(FE) in the structure illustrated inFIGS. 5 and 6 as compared to the conventional structure illustrated inFIGS. 1 and 2.

What is claimed is:
 1. A method of manufacturing a semiconductor devicewhich includes a bipolar transistor having at least an emitter region,comprising the steps of: forming an emitter electrode on said emitterregion; forming an insulating layer on said emitter electrode; forming aplurality of contact holes in said insulating layer; embedding aplurality of contact plugs in the contact holes; and forming a wiringpattern on said insulating layer.
 2. A method as claimed in claim 1 ,wherein: said contact plugs are partially embedded in said emitterelectrode.
 3. A method as claimed in claim 1 , wherein: said bipolartransistor has a predetermined current amplification factor, and saidcontact plugs are formed in order to prevent reduction of the currentamplification factor.
 4. A method as claimed in claim 1 , wherein: eachof said contact plugs is formed by tungsten, said emitter electrode isformed by a polysilicon, and said wiring pattern is formed by aluminum.5. A method as claimed in claim 1 , further comprising the steps of:forming an epitaxial layer on a silicon substrate; and forming saidemitter region in said epitaxial layer.
 6. A method of manufacturing aBiCMOS semiconductor device which includes a CMOS transistor which hasat least source and drain regions and a bipolar transistor which has atleast an emitter electrode and which is arranged adjacent to said CMOStransistor, comprising the steps of: forming a first insulating layer onsaid CMOS transistor; forming a second insulating layer on said bipolartransistor; forming a first contact hole in said first insulating layer;forming a plurality of contact holes in said second insulating layer;embedding a first contact plug in said first contact hole; embeddingsecond contact plugs in said second contact holes; forming a firstwiring pattern on said first insulating layer; and forming a secondwiring pattern on said second insulating layer.
 7. A method claimed inclaim 6 , wherein: the height of said second insulating layer is smallerthan that of said first insulating layer.
 8. A method claimed in claim 6, wherein: the height of said second contact plug is smaller than thatof said first contact plug.
 9. A method as claimed in claim 6 , wherein:said first contact plug contacts with a surface of either one of saidsource and drain regions while said second contact plugs are partiallyembedded in said emitter electrode.
 10. A method as claimed in claim 6 ,wherein: said bipolar transistor has a predetermined currentamplification factor, and said second contact plugs are formed in orderto prevent of the current amplification factor.
 11. A method of making asemiconductor device that includes a bipolar transistor formation regionhaving an emitter diffusion region and a CMOS transistor formationregion having a source/drain diffusion region, the method comprising thesteps of: forming an interlayer insulator over the emitter diffusionregion and the source/drain diffusion region, the interlayer insulatorbeing thicker over the source/drain diffusion region than over theemitter diffusion region; forming a first contact plug that extendsthrough the interlayer insulator into contact with the source/draindiffusion region; forming plural second contact plugs that extendthrough the interlayer insulator into contact with the emitter diffusionregion, the plural second contact plugs being directly over the emitterdiffusion region so that the plural second contact plugs overlap theemitter diffusion region; forming a first wiring layer over theinterlayer insulator over the source/drain diffusion region, the firstwiring layer contacting the first contact plug; and forming a secondwiring layer over the interlayer insulator over the emitter diffusionregion, the second wiring layer contacting the plural second contactplugs.
 12. The method of claim 1 , wherein the plurality of contactholes are formed directly over the emitter region so that the pluralityof contact plugs overlap the emitter region.
 13. The method of claim 6 ,wherein the plurality of second contact holes are formed directly overthe emitter region so that the second contact plugs overlap the emitterregion.